1. Field
This disclosure relates generally to phase interpolator circuits, and more specifically, to a double-balanced sinusoidal mixing phase interpolator circuit and method.
2. Related Art
In high speed serial data communications, clock and data recovery (CDR) must be performed on a noisy input data stream before corresponding data can be further processed by a digital system. Generally, in a digital core based clock recovery system, a reference clock signal of a given frequency can be generated together with a number of different clock signals having the same frequency but with different phases. For example, the different clock signals can be generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
In another implementation, a single interpolator is comprised of N current sources that are selectively turned on or off, in accordance with an applied M bit interpolation control word, to mix two clock signals of fixed phase difference to obtain a desired clock phase. The desired clock can have its synthesized phase falling anywhere discretely between the two fixed input clock phases. The performance of clock recovery circuit highly relies on how fine and how uniform the interpolator can generate the desired clock phase.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.